Designer Perpignan : Trouvez vite les meilleurs freelances disponibles

Exemple de missions de Davide,
freelance

• Function: ASIC RTL Designer Engineer

  Company: Qualcomm UK
  Jan 2020 - Jan 2020

  Subject: Supporting the ASIC RTL team for the IoT audio system development of a smart
  wearables technology. Involved in all the different ASIC steps.

  Technical Environment: Linux, Windows NT, Synopsys, SpyGlass, VCS, Clearcase, Visio.

• Function: ASIC RTL Designer Engineer

  Company: Ericsson – Sweden & UK
  Jan 2017 - Jan 2020

  Subject: Supporting the ASIC RTL team for the 5G system development. In charge for the BB &
  Radio Controller Subchips & Subsystems Integration (CCCR, EVC, GPIO_CTRL, SPI, LED,
  Synopsys I3C Master & Slave DW IPs, PA_CTRL, SYNC, AXI_CTRL_UART, DB_UART, NIC400).
  RTL development and modification of internal IPs and Filters Dynamic Power Save
  optimization. Writing Design Specification documentation. Supporting verification &
  validation.

  Technical Environment: Linux, Windows NT, Cadence, Synopsys, Clearcase, SpyGlass, Spectre, Visio, Wavedrom, Hansoft Agile, Mantis.

• Function: ASIC Designer Engineer

  Company: Ensilica – London
  Jan 2017 - Jan 2017

  Subject: Supporting the ASIC team going to the tape-out for a mixed-signal ASIC.

  Technical Environment: Linux, Windows NT, Cadence

• Function: ASIC RTL Designer Engineer

  Company: Confidential – Italy
  Jan 2016 - Jan 2016

  Subject: Supporting the RTL design team for the front-end ASIC design flow
  Activities: Writing design specifications, RTL conception and Verilog development of:
  asynchronous interfaces for fast data exchange – data path blocks – RTL modifications
  for Power optimization - blocks integration – block level testbench – simulation –
  synthesis scripts

  Technical Environment: Unix, Windows NT, Cadence, Synopsys

• Function: ASIC Digital Designer Engineer

  Company: Contractor in S3 Group – Prague - CZK
  Jan 2015 - Jan 2015

  Subject: Supporting the RTL design team for the development of a mixed-signal fingerprint SoC
  ASIC based on Cortex-M0
  Activities: Writing design specifications, RTL conception and Verilog/System Verilog
  development of: clock/reset/power management unit - dft controller - modules
  modelling - digital thermometer - srams integration

  Technical Environment: Unix, Windows NT, Cadence, SVN, ClearCase, Visio, Wavedrom

• Function: ASIC Digital Designer Engineer

  Company: Contractor in Imagination Technologies IMGTEC – London - UK
  Jan 2014 - Jan 2015

  Activities: Supporting the Video H265 Encoder RTL design team for the ASIC design flow, VHDL
  Also Supervisor of main activities and designers

  Technical Environment: Unix, Windows NT, Cadence, Synopsys, P4V, Jenkins

• _ASIC Digital Designer Engineer

  Jan 2013 - Jan 2013

  Company: Confidential
  Activities: RTL development and VHDL coding of a JPEG Encoder with Pipelined Parallel
  Architecture.
  Technical Environment: Unix, Windows NT, Cadence

  Technical Environment: Unix, Windows NT, Cadence

• Function: ASIC/FPGA Designer Engineer

  Company: ASTEK Consulting Group / NXP-Philips in Sophia Antipolis - France
  Jan 2007 - Jan 2008

  Subject: Consultant in NXP-Philips to support the RTL design team developing sub-blocks for a
  Bluetooth digital receiver.
  Activities: Old architecture improvement - data bus control interface, Clocks & Power management
  unit RTL conception and VHDL development - Top level integration - test bench
  development - simulation - Top porting and Quartus synthesis on Altera FPGA -
  drawing up user manual and release document

  Technical Environment: Unix, Windows NT, Cadence, Quartus Altera FPGA

• Jan 2000 - Jan 2006

  Company: STMicroelectronics in Milan-Italy
  Function: ASIC Digital Designer Engineer
  Activities:
  -Responsible for: proprietary AS-DSP micro-architecture RTL development, peripherals, IPs and SoC
  subsystems conception and implementation for different customers: cores, cache memories, TCM,
  Memory-Bists, Bus, Peripherals.
  -Conception and development of a Co-Processor for the fft, Hardware Accelerators for Data Path.
  -ARM cores and peripherals SoC implementation: A7s, A926, A946, L210 cache-controller, AMBA.
  -IP blocks conception, implementation and verification, top-level integration for System-on-Chip,
  typical peripherals: FIFO, Event-Counter, Frequency-Capture, Timer, GP-IO, Serial&Parallel-IO,
  I2S, I2C, Interrupt-Controller, PWM/PDM/Stepping Motor-Control, Watch-Dog, Mailbox, Bridges,
  Devices-Wrappers, Clock/Reset/Power Manager.
  -Multimedia SoC Platform for NOKIA Mobile (NOMADIC): Core Subsystem RTL development and
  implementation.
  Involved in the Front-End design flow:
  -RTL conception, VHDL & Verilog development
  -Test-bench development, RTL simulation
  -Synthesis (internal Clock-Gating, memory Bist, Scan Chains insertion, ATPG coverage)
  -Formal Verification RTL-Gate
  -Gate-Level simulation
  -Different technologies synthesis: High Speed, Low-Power, High Density
  Partnership:
  - Motorola and Texas Instruments: to test new Low-Power and High-Density technologies, multiple
  synthesis tests ACCENT: to develop subsystems for a Smart-Sensor-Device

  Technical Environment: Main SYNOPSYS and CADENCE design tools for synthesis, simulation and verification: Synopsys: Design Compiler (Chip Synthesis) Physical Compiler (Cell Placement) Formality (Equivalence Checking) Primetime (STA) TetraMAX (ATPG – Patterns Generation) VSS (Simulation) Cadence: NC-Sim, compiling Mentor-Graphics: Model-Sim Assembly Unix, Windows NT, main Windows Software as Office (Word, Excel, PowerPoint)