Missions VHDL : Une multitude d'offres déposées toutes les semaines

Exemple des emplois de Davide,
freelance VHDL habitant les Alpes-Maritimes (06)

_Principal ASIC RTL Designer - Freelance
_Ericsson - remote
juin 2024 - mai 2025
Subject: Many-Core Architecture (EMCA) : scalable and energy efficient Radio-AccessNetwork (RAN) parallel compute networks for 5G/IoT. In charge for the RTL
development of innovative new features to improve multi-channels communication
between multiple CPUs / DSPs / Accelerators. I validated my implemented
microarchitectures through linting, sim debug and supporting the verification team to
correctly tune their testcases through the analysis of their failing tests. Project
specific documentation update.
Technical Environment: Linux, Windows NT, SpyGlass, Synopsys, Cadence, Modelsim,
Simvision, GIT, Visio, SystemVerilog, VHDL, AMBA AXI-ACE.

_Principal ASIC RTL Designer - Freelance
_Infineon - remote
2022 - 2023
Subject: SoundWire-I3S (SWI3S) Peripheral IP: In charge for the IP architecture conception
and RTL development of all the modules of the new MIPI Audio Interface Peripheral
unit used for transporting audio streams and control information frames together on a
single link in half/duplex fashion, single-ended PHY: Link-Controller, CommandTransport-Decoder, Payload-Controller for Audio Chip. Participating also to the
system validation through linting, debug and supporting the verification team to
correctly tune their testcases through the analysis of their failing tests. Participated to
the review of multiple MIPI Draft SWI3S draft specifications.
Project specific documentation update in Jama.
Technical Environment: Linux, Windows NT, SpyGlass, Cadence, Modelsim, Clearcase, GIT,
Jira, Visio, Jama, SystemVerilog.

Function: Principal ASIC RTL Designer - Freelance
Company: Infineon - remote
2021 - 2022
Subject: Time-of-Flight 3D Camera project: In charge for the RTL development of the new
DVGA-Sensor-Matrix Readout Control unit and Exposure Control unit: controllers
for ADC, Sensor, DAC and Exposure. Plus RTL development of a Motion Detection
support unit, compensation of ADCs results. Improvements of: existing
memory controller for a new access mode for the mems ping-pong and a Frequency
ramper generator. Participating also to the validation of my developed RTL through
linting, debug and supporting the verification & firmware teams to correctly build
their testcases and FW codes involving my modules through the analysis of their
failing tests. Documentation update
.
Technical Environment: Linux, Windows NT, Synopsys, SpyGlass, Cadence, Modelsim,
SuperLint, Clearcase, Jira, Visio, Jama, SystemVerilog.

Function: Principal ASIC RTL Designer - Freelance
2021 - aujourd'hui
Company: Confidential - remote
Subject: Part-time freelance collaboration supporting the Digital ASIC team for RTL
development-supervisor for concept improvement of my previous design project, 5G.
Technical Environment: Linux, Windows NT, Synopsys, SpyGlass, Cadence, Clearcase,
Visio, SystemVerilog.

_Principal ASIC RTL Designer - Freelance
_Qualcomm - remote
2020 - aujourd'hui
Subject: Supporting the ASIC RTL team for the IoT audio system development of a smart
wearables technology. Involved in all the different ASIC flow steps. SoC with ARM
Cortex-M3 core.
Technical Environment: Linux, Windows NT, Synopsys, SpyGlass, Cadence, Clearcase,
Visio, Verilog & VHDL.

2017 - 2020
Company: Ericsson - remote
Function: Principal ASIC RTL Designer - Freelance
Subject: Supporting the IP & Radio-Controller team for the 5G system RTL development
of four chips.
In charge for the RTL new development or optimization/modification of existing IPs:
Event-Controller core, Filters Dynamic Power Save optimization, CCCR, EVC,
GPIO_CTRL, SPI, LED, Synopsys I3C Master & Slave DW, PA_CTRL, SYNC,
AXI_CTRL_UART, DB_UART, NIC400. Implementation of the four BaseBand &
Davide ******** CV - 2025
Radio Controller Subchips & Subsystems including the above IPs. Writing Design
Specifications documentation. Supporting verification & validation involving my
modules.
Technical Environment: Linux, Windows NT, Cadence, Synopsys, Clearcase, SpyGlass,
Spectre, Visio, Wavedrom, Hansoft Agile, Mantis, SystemVerilog &
VHDL.

_Principal ASIC Designer - Freelance
_Ensilica
2017 - aujourd'hui
Subject: Supporting the ASIC team going to the tape-out for a mixed-signal Fingerprint ASIC
SoC with ARM Cortex-M3 core.
Technical Environment: Linux, Windows NT, Cadence, Verilog & VHDL.

_Principal ASIC RTL Designer - Freelance
_Confidential
2016 - aujourd'hui
Subject: Supporting the RTL design team for the front-end ASIC design flow
Activities: Writing design specifications, RTL conception development of:
asynchronous interfaces for fast data exchange – data path blocks – RTL
modifications for Power optimization - blocks integration – Supporting validation
Technical Environment: Unix, Windows NT, Cadence, Synopsys, SystemVerilog & VHDL

_Principal ASIC RTL Designer - Freelance
_S3 Group
2015 - aujourd'hui
Subject: Supporting the RTL design team for the development of a mixed-signal fingerprint
SoC ASIC based on ARM Cortex-M0 core.
Activities: Writing design specifications, RTL conception and development of:
clock/reset/power management unit - dft controller - modules modelling - digital
thermometer – Macro with srams integration
Technical Environment: Unix, Windows NT, Cadence, SVN, ClearCase, Visio, Wavedrom,
Verilog & VHDL.

Function: Experienced ASIC Digital RTL Designer Engineer - Freelance
2008 - aujourd'hui
After my last experience as permanent consultant I became interested in working as Freelancer in
Europe in parallel, after a marketing investigation in the south of France, I spent my energy in
trying to create a business activity in order to help the semiconductor companies to develop their
ASIC systems.
I also worked developing my own modules to sell directly to the clients, as :
• 1Gb DDR2 SDRAM controller
• Data-Link-Layer for the PPP Protocol frames over Ethernet (PPPoE) RFC-2516, Sw/Hw trade-off
Currently Independent Freelancer, used to work closely with management, often involved in
customer meetings. Expert in the area of RTL IPs conception and development for ASIC & SoC,
with particular attention to Power/Speed/Area optimization typically:
• IP architecture conception
• Hardware accelerators for data-path
• Pipeline Architectures
• Smart Finite-State-Machines for algorithms development, functions and data-conditioning
• Asynchronous interfaces, generic or customized fast interfaces solutions
• IPs Low power architectures
Hereinafter latest meaningful completed contracts: