Freelance VHDL : Recevez gratuitement les CV qui vous intéressent

Résumé des missions de Fraidy,
freelance VHDL habitant l'Isère (38)

Expérience professionnelle

Octo 2019 – today
3 years 1 month
Part-time Lecturer at University of Marien NGOUABI
One trimester by year
Courses: Digital electronic, Signal Processing, Computer architecture
Level: Bachelor’s degree Master’s degree.

Dec. 2019 – June 2021
1 year 7 months
Consultant as a senior Digital Designer for Cogito Instruments SA
Working as a freelance with Cogito Instruments on the development of a neural circuit: pattern learning
and classification
- SystemVerilog/VHDL
- Testbench
- FPGA flow (Xilinx)

Oct 2017 – Dec 2018
1 year 3 months
Deputy Director of Technical/Marketing Strategy – DOLPHIN DESIGN
In charge of :
- business development of microcontroller subsystems (RISC-V),
- marketing and promotion Strategy,
- development of strong innovative culture within the company focused on customers,
- Driving the communication and digital marketing yearly plan,
- Managing press release, collaterals and communication budget,
- Coordination product communication campaigns and participation at industry events and trade
show,
- Evaluation and reporting on the KPIs
Joseph Fourier University: Part-time lecture.
- Professional master’s degree: VHDL language
- Bachelor’s Degree in science and Technology: Digital systems

Sept 2015 – Oct 2017
2 years 2 months
Contributor/Expert in Micro & nano electronic – TIMA Laboratory
Expert in IC-design conception
- Conception of a robust LEON3 microprocessor for reliability.
- Double sampling methods improvement
- Prototyping in FPGA of LEON3
- Test and qualification
Part-time lecturer
Joseph Fourier University
(45 hours/year)
- Professional master’s degree: VHDL language
- Bachelor’s Degree in science and Technology: Digital systems
Grenoble Institute Of Technology and Grenoble University
(30 hours/year)
- Digital system fundamentals
- Introduction to digital design.
- VHDL design flow.
- Fast prototyping with FPGA: Altera and Xilinx

March 2014 – June 2015
1 year 4 months
Consultant as a Security Manager - TIEMPO SAS
In charge of the common criteria and EMVCo certification processes of Tiempo’s secured circuits.
- Specification of hardware (software) countermeasures against threats.
- Securing the working environment including network and IT processes.
- Writing of common criteria documents. Security target, Development architecture documents.
- The following of the circuit evaluation done by the laboratory licensed by the French Network
and Information Security Agency (ANSSI in French).
Part-time lecturer
Grenoble Institute of Technology and Grenoble University
(30 hours/year)
- Digital system fundamentals
- Introduction to digital design.
- VHDL design flow.
- Fast prototyping with FPGA: Altera and Xilinx

Janu 2013 – March 2014
1 year 3 months
Security Manager – TIEMPO IC
Security Manager in charge of CC and EMVCo certification of TIEMPO secure products.
- Specification and implementation of the secure development area. It includes the writing of
secure procedures and policies.
- Development CC documents: Security Target, Development ....
- Specification and design of secure products.
Part-time lecturer
Grenoble Institute of Technology and Grenoble University
(30 hours/year)
- Digital system fundamentals
- Introduction to digital design.
- VHDL design flow.
- Fast prototyping with FPGA: Altera and Xilinx

Dec 2007 – Dec 2012
5 years 1 month
Integrated Circuit Design Architect - TIEMPO IC
Design architecture engineer of asynchronous and synchronous integrated circuits.
- Implementation of DPA platform
- Design specification and implementation of a secure asynchronous RSA crypto-processor
(based on Montgomery theory) and compliant to ECC in GF(p).
- Design specification and implementation of a secure asynchronous 16-bit microcontroller
- Design specification and implementation of a secure asynchronous DES crypto processor.
- Design specification and implementation of a synchronous DES crypto processor.
- Specification and conception of test cards based on FPGA for testing.
- Patent publication on delay insertion in quasi-delay insensitive asynchronous design.
Part-time lecturer
Grenoble Institute of Technology and Grenoble University
(30 hours/year)
- Digital system fundamentals
- Introduction to digital design.
- VHDL design flow.
- Fast prototyping with FPGA: Altera and Xilinx

Sept 05 – Aug 06 Temporary Lecturer and Research Assistant - PHELMA (Physics, Applied Physics,
Electronics & Materials Science)/ex-ENSERG
- Research on hardware security and asynchronous logic.
- Teaching design modelling, methodology of conception, VHDL language, simulation and cosimulation, and digital systems.

OTHER EXPERIENCES

April 14 - today Consultant in Marketing and strategy:
INSG-CG: Survey Institute in Congo (Brazzaville)
- Support to the establishment
- Business strategy
- Marketing strategy and communication
- Prospect research

AIRCOTECH-CG: air-conditioning systems in Congo (Brazzaville)
- Support to the establishment
- Business strategy
- Marketing strategy and communication
- Prospect research

July 15 – Octo 15 Consultant in Marketing and strategy:
ALSUN (Suisse): Market research in landscaping.

Involving in different research and development projects:
2002-2005 - RNRT-DURACELL Project: The objective was to evaluate the asynchronous logic against fault
injection attacks.
2003-2005 - Research project with the General Secretariat for Defence and National Security (SGDSN): The
objective was to evaluate against hardware attacks an asynchronous AES circuit.
2001-2004 - IST-G3CARD European Project: Third generation of smartcard in asynchronous logic
Following my participation to these projects, I have designed 6 prototyping circuits in synchronous and asynchronous
logics:
- Conception of a multiply-divide unit (MDU) for a MIPS4ks.
- Conception of 3 DES crypto processors: a reference one, low power consumption version and a secured
version.
- Conception of 2 AES-128 crypto-processors: a low power one and a secured version.

Training, Management and Publications:
- FPGA Prototyping using hardware description language (VHDL).
- Workshop on design conception.
- Embedded System Design: Modeling, Synthesis and Verification.
- Internship supervisor in master’s degree in digital and analog integrated circuit design.
- Technical paper reviewer.
- Organization of international conference: ACID 2002 and ASYNC 2006.
- 22 scientific publications with 1 book chapter, 1 review, 14 papers in international conferences, 2 papers in French
conferences and 4 invited papers in international conferences.