Missions XILINX : Une multitude d'offres déposées toutes les semaines

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Les dernières missions XILINX à pourvoir

Développeur FPGA

FPGA
ASAP
75 - Paris
6 mois
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Ingénieur FPGA

FPGA
ASAP
06 - VALBONNE
12 mois
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Designer FPGA VHDL

VHDL FPGA Electronique Python XILINX
ASAP
06 - SOPHIA ANTIPOLIS
18 mois
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Consultant Electronicien FPGA

FPGA VHDL
ASAP
06 - Valbonne
6 mois
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Développeur FPGA Xilinx

XILINX
ASAP
75 - PARIS
2 mois
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Développeur VHDL / FPGA Zynq US+

VHDL FPGA XILINX
ASAP
92320
6 mois
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INGENIEUR ELECTRONIQUE NUMERIQUE FPGA H/F sur Toulouse

VHDL Linux embarqué FPGA XILINX
ASAP
31
6 mois
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Développeur XILLINX

C++ XILINX SPARTAN FPGA
ASAP
38 - Grenoble
3 mois
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Je trouve ma mission XILINX

Les intervenants XILINX ont aussi candidaté à :

Développeur - Systèmes embarqués

C++ Linux Python Git
ASAP
BEZONS
6 mois
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Ingenieur FPGA SOC ASIC

FPGA VHDL
ASAP
75
3 mois
Voir la mission

Développeur(euse) Embarqué C/ FPGA (H/F) sur Rennes

FPGA C EMBARQUE
ASAP
Cesson-Sévigné
3 mois
Voir la mission

Développement bibliothèque Arduino de gestion USB

USB Arduino C++
ASAP
Neuilly sur Seine
14 jours ouvrés
Voir la mission

Développeur C++ / Arduino

C++ Arduino
ASAP
Télétravail
3 jours ouvrés
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Développeur VHDL

VHDL
ASAP
38 - Grenoble
2 mois
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Consultant Formateur VHDL

VHDL
A définir
13 - Marseille
6 jours ouvrés
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Ingénieur VHDL

VHDL
ASAP
75 - Paris
3 mois
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Ingénieur VHDL

VHDL
ASAP
67 - Strasbourg
3 mois
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Développeur VHDL

VHDL
ASAP
16 - Angoulême
2 mois
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Je trouve ma mission XILINX
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Exemple d'expériences de Souhail,
freelance XILINX habitant le Val-d'Oise (95)

Experience

OSMOS-GROUP PARIS 16, France
SENIOR EMBEDDED SOFTWARE ENGINEER 13 July 2023- today
• LIRIS-V3 Porject: OSMOS has developed a range of structural health monitoring solutions. Among them, they
designed autonomous sensors called LIRIS, that are installed on key points of the structure to measure the effects
of deformations, cracks, bearing conditions or external stresses. The main tasks that I have conducted are:
– Maintaining the LIRIS_V3 source code: bug fix and new features implementation.
– Implement and test the LIRIS-420mA module.
– Integrate the crack-Meter module.
– Integrate an SMS module.
– Implement low lovel driver for ADC and DAC based on SPI interface.
– Implement a driver for the Lora-Grove to synchronize LIRIS for OSMOS WIM+D uses case project
– Programming Languages used : C
– Software environment: Keil, JLink, GitLab
– Hardware environment: nRF52832 cortex M4

• LIRIS LTE-M/Nb-iot: In order to reinforce the aspect of autonomous sensors, OSMOS has developed an extension
board that host an LWM2M client module which uses LTE-M/Nb-iot technologies to communicate with the server.
The main tasks that I have conducted are as follow:
– Participate in specifications elaboration.
– Definition of the software architecture.
– Define the project skeleton based on zephyr OS project.
– Implement driver to communicate with the LIRIS-V3 via asynchronous interface.
– Implement the LWM2M client side with customized objects.
– Reduce power consumption with respect to the specifications.
– Implement a flusk based micro-server with python.
– Programming Languages used : C, python, Makefile
– Software environment: Zephyr, MC-UBOOT, Arm-GCC, GDB, JLink, GitLab
– Hardware environment: nRF9160 cortex M33

ZOOV Vanves, France
EMBEDDED SOFTWARE ENGINEER Mars- June .2020
• Implementation from scratch of an LWM2M stack based on the Zephyr OS Coap library.
• Functional requirement specification.
• Software architecture design.
• Porting the Zephyr OS Coap library
• Programming Languages used : C
• Software environment: gcc, MakeFile, Kconfig, FreeRtos, JLink, GitHub
• Hardware environment: nRF52840 cortex M4
OCTOBER 12, 2022 CLAUD D. PARK · CURRICULUM VITAE 2
Embedded Software Engineer Suresnes, France
SMARTO SAS Feb. 2020 - Now
• Implementation of a vehicle fleet management solution through the addition of LoRaWAN connectivity to the
CarAlgo dongle.
• Functional requirement specification.
• Software architecture design.
• Porting the Semtech LoRaMac stack 4.3.3
• Programming Languages used : C
• Software environment: Mcuxpresso, FreeRtos, Objenious, JLink, GitLab
• Hardware environment: NXP-kinetis cortex M0+, Semtech sx1272

Embedded Linux Engineer SMARTO SAS Suresnes, France
ANAIS HDMI/USB STICK DONGLE May. 2019 - Jan. 2020
• Design and implementation of a secured mini stick HDMI/USB dongle named ANAIS for presentation and video
play uses.
• Functional requirement analysis.
• Task, kernel side:
– Building customized linux kernel distribution (modification of Makefile, Kconfig and device tree files).
– Generating root file system.
– Customize spl and u-boot for the target supported Bsp.
– Integration of the fingerprint driver.
• Tasks, Application side:
– Software architecture design.
– Developing an application based on Bluez, to remotely interact with the Anais dongle via Ble connectivity.
– Adding a desktop daemon service to handle multimedia functionalities.
– Developing an application to lock and unlock the Anais dongle using the fingerprint module.
– Development of an application for the battery charge display managemen.
• Software environment: Gnu Linux eco-system, Makefile, C, shell
• Hardware environment: Beaglebone black, SIP Octavo osd335x, TI Wl18xx.

Embedded Software Engineer SMARTO SAS Suresnes, France
CARALGO OBD-BLE DONGLE Sep. 2018 - Apr. 2019
• Implementation of an OBD dongle device for connected vehicles application.
• Define functional requirements and specifications.
• Software architecture design.
• Implementation of a BLE protocol to exchange with smartphone devices
• Developing device driver (External flash memory, Accelerometer).
• Implementation of an approach to redirect the three axis of the accelerometer using quaternions rotation matrix
• Programming Languages used : C
• Drafting of technical requirements and constraints.
• Software environment: Mcuxpresso, FreeRtos, JLink, GitLab
• Hardware environment: NXP-kinetis cortex M0+

OCTOBER 12, 2022 CLAUD D. PARK · CURRICULUM VITAE 3
Embedded Linux Engineer SMARTO SAS Suresnes, France
VISIOWATCH Feb. 2018 - Aug. 2018
• In cooperation with Quicklogic and SierraWirless, I participated in the software design and implementation of a
connected watch to remotely monitor elderly patients
• Functional requirement analysis.
• Task, kernel side:
– Building customized linux kernel distribution Using Yocto project.
– Integrate SPI driver of the Quicklogic EOS3 chip.
– Integrate SDIO/UART driver of the TI WL18xx wifi/Ble module.
• Tasks, Application side:
– Software architecture design.
• Software environment: C, Yocto, shell, bitbake, ssh, VIM, linux kernel
• Hardware environment: SIP WP7607, GPP EOS3 module Wifi/Ble Wl18xx.

Embedded Software Engineer SAGEMCOM SOFTWARE &
TECHNOLOGIES, Tunisia
SMART METERING Sep. 2016 - Dec. 2017
• Functional requirement analysis.
• Tasks:
– Correct bugs, participate to new feature design and implementation, elaborate and execute unit and integration tests.
• Programming Languages used : C/C++and Python.
• Platform : Smart Meters with the following communication protocols : MBUS, WMBUS, G3 PLC, PRIME, etc...
• MCUs : STM32F4xx, STM32F1xx and STM32F0xx.
• Clients : Enedis, Enexis, Lux.

Assistant Teacher Facultè des Sciences de Bizerte,
Tunisia
Sep. 2015 - Jun. 2017
• The assistant teacher role in Tunisia is different than elsewhere. A TA is allowed to teach courses and participate
in the academic life as a full faculty member.
• Taught the following courses :
– Hardware Description Languages for FPGA Design.
• Taught the following labs :
– C programming, VHDL, Embedded Systems Programming STM32, Digital Signal Processing(Matlab).

Assistant Teacher High Engineering School of Tunis
(SUP’COM), Tunisia
2013 - 2015
• Taught the following labs :
– Programmable circuits (VHDL), Embedded Processor (ARM7), LabView and Tutored Projects.

OCTOBER 12, 2022 CLAUD D. PARK · CURRICULUM VITAE 4
Undergraduate Research Tunis, Tunisia
GREEN AND SMART COMMUNICATION LAB(SUP’COM) 2013 - 2017
• Hardware architecture of multipath MIMO channel emulator for Mobile-To-Mobile systems
– High level synthesis of a hardware architecture for MIMO Mobile-to-Mobile channel emulation( C/C++, VivadoHLS, Xilinx Zynq).
– Cuda GPU acceleration of a MIMO Mobile-to-Mobile channel simulator (CC++, Cuda 8.0, parallel computing).
– Co-design and implementation of an IP for random Gaussian number generation on Xilinx Zync FPGA.
• Publications :
– ********, Souhail, et al. ”A novel filter-based model for mobile-to-mobile double-Rayleigh fading channels.”

2016 International Symposium on Signal, Image, Video and Communications (ISIVC). IEEE, 2016.
– ********, Souhail, et al. ”A flexible filter-based Mobile-to-Mobile Double Rayleigh Fading channel emulator.”
2016 5th International Conference on Multimedia Computing and Systems (ICMCS). IEEE.
– ********, Souhail, Fatma Rouissi, and Fethi Tlili. ”An Autoregressive Model for Mobile-to-Mobile Rayleigh Fading Channel Simulation.” Journal of Communications 13.1 (2018).
– ********, Souhail, et al. ”A compact architecture of a Mobile-to-Mobile fading channel emulator based on
Random Walk Process.” 2016 5th International Conference on Multimedia Computing and Systems (ICMCS).
IEEE.
– ********, Souhail, et al. ”Gaussian random number generator design based on double non-uniform segmentation.” 2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS). IEEE, 2015.
– ********, Souhail, et al. ”Improved simulation model for mobile to mobile rayleigh fading channels based on
random walk process.” International Conference on Software Telecommunications and Computer Networks
(SOFTCOM), Workshop on Information and Communication Technologies. 2015.
– ********, Souhail, Imèn Debbabi, and Fethi Tlili. ”Enhanced implementation of morphological operators on
a synthesizable ASIP.” 2014 International Conference on Multimedia Computing and Systems (ICMCS). IEEE,

2014.
Education
Green and Smart Communications Laboratory (GRESCOM, SUP’COM) Tunis, Tunisia

MSC IN COMMUNICATIONS: CIRCUITS

Systems of
Telecommunications
Sep. 2011 - Jun. 2013
• Enhanced implementation of morphological operators on a Synthesizable ASIP
– CoDesign and implementation of an IP to speed up the computation of morphological operators (VHDL,
Xilinx Virtex V).
– Integrate the IP in a 32-bit softcore GPP processor (Plasma softcore).
– Add instructions to the MIPS I toolchain compiler (gcc, Crosscompiling).
Higher Institute of Computer and Multimedia of Sfax, ISIMS Sfax, Tunisia
COMPUTER ENGINEER Sep. 2008 - Jun. 2011
• End of studies project :
– High level characterization and optimization of a GPSK modulator with Genetic algorithm.

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