Freelance MODELSIM : Sélectionnez gratuitement les meilleurs CV

Exemple des missions d'Abdelhakim,
freelance MODELSIM habitant les Alpes-Maritimes (06)

• Jan 2013 - Jan 2013

  Réalisation(s) :
  
  Conception de l'environnement de verification ( Testbench et testcases en VHDL) pour un USB Redriver chez NXP Belgique à Leuven.

• <Texas Instruments>
  Jan 2012 - aujourd'hui

  Réalisation(s) :
  
  Scripting en TCL et automatisation du flot de conception de l’IP PRCM (Power Reset Clock Management) pour omap6430 platforme ) pour conception ASIC.
  synthese DC synopsys et RC cadence ( generation du RTL structurel et application des contraintes de timing a partir des specifications.)
  LEC (equivalence checking)entre RTL et netlist de synthese,
  spyglass d Atrenta (pour detection de problemes de communications de domaines de clocks, bad RTL coding detection ,etc..)

• Support Technique au groupe support Client

  <PLDA>
  Jan 2011 - Jan 2012

  Réalisation(s) :
  
  Apprentissage en detail des Specifications USB3.0, ( partie physical Layer, Link Layer, protocol Layer, xHCI).
  Débugage du Verilog IP USB Device que ce soit dans la partie Link Layer et protocol Layer, Codage Verilog, simulation ncsim et Modelsim, synthèse FPGA Altera, analyzer LeCroy pour enregistrement Packets USB….

• Texas Instruments, Villeneuve-Loubet, France
  Jan 2006 - aujourd'hui

  Integration Project Attila
  - Integration (ASIC CMOS 0.21um) OMAP Architecture. Responsible for equivalence checking…
  
  Integration Project Wrigley3g
  - Integration (ASIC CMOS 0.21um) OMAP Architecture. Application Image processing and Voice for phone cells. RTL Assembly. , ECO scripting, equivalence checking
  
  Integration project Neptune3g2
  - Integration (ASIC CMOS 0.21um) OMAP Architecture. Application Image processing and Voice for phone cell. RTL Assembly (complexity 40000 signals)(with SPIDER of Duolog) et Bug Tracking (Rational clearQuest, IBM), Power Management (isolation Power domain). ClearCase for File Management¦

• Schneider Electric, Sophia Antipolis, France
  Jan 2005 - Jan 2005

  Full time Eng. Consulting ALTIOR in Schneider.
  - Specification (chronogramme TimingDesigner), Verilog Coding & simulation (NC-Verilog Cadence) of an Asynchrone Dpram
  - Selection of Uart IPs

• Schneider Electric, Sophia Antipolis, France
  Jan 2004 - Jan 2005

  Full Time Eng. Consulting ALTIOR in Schneider for the Design of an ASIC 0.25u NEC
  - Contribution for the architecture of a Private Bus Microcontroler ,
  - Coding of various modules (Verilog),
  - simulation (NC-Verilog Cadence) & cosimulation in C
  - ASIC Test integration in C embedded.
  - Use of Synopsys FORMALITY Tool for formal verification,
  - File Manager gCVS

• SAN Valley Systems, Campbell, CA 95008, USA
  Jan 2001 - Jan 2001

  Design and specification of the network interface for a FCIP storage area network (SAN) products.
  
   Senior ASIC Architect/Designer
  - Specification & Design of TCP/IP in hardware.
  - Study & state of the art for real time techniques applied for iSCSI protocol
  
   Project Leader/Architect
  - Design & specification of the Network interface for FCIP storage area network (SAN)

  Technical Environement : Hardware DDR RAMs, PowerPC IBM, FPGA Xilinx

• ALCATEL (Packet Engines), Spokane, WA , USA
  Jan 1999 - Jan 2001

  Design of the ASIC part for internet router
   ASIC Designer
  - Functional Simulations with NC_Verilog for the validation of a Network Processor 2 gigabit.
  - Architectural Design for a high-speed 20 gigabit "search engine".
  - Contribution for the study of the feasibility of a 40 gigabit Network Processor.
  - Study of the IP cores CPU (ARM, MIPS) in the market

  Technical Environement : Technology ASIC 0.25u CMOS, Différent modules, CPU maison type ARM Languages Behavioral Verilog Tools Verilog-NC (cadence)

• Genesis, Markham Canada
  Jan 1997 - Jan 1999

  Design of an ASIC for video application (projector, flat panel display)
  Senior Eng.
  - Coding in VHDL for an ASIC CMOS 0.25u, Simulation with Modelsim MTI and Synthesis & STA with Synopsys Design Analyzer. Design of Memory Controler & FIFO,
  - Coding in VHDL for an ASIC CMOS 0.18u IBM, Simulation with Modelsim MTI and Synthesis & STA with Synopsys Design Analyzer. Design of the Host, etc…

  Technical Environement : Technology ASIC CMOS 0.25u,ASIC CMOS 0.18u Languages VHDL Tools Modelsim, Synopsys

• Senior Designer

  Morphometrix Technologies, Toronto, Canada
  Jan 1995 - Jan 1997

  - Implemented several FPGAs for a system that performed automated analysis of pap smear tests. Worked with Altera.
  - Also designed a PCI data acquisition board.

  Environnement Technique : Technology FPGA’s Altera (serie 8000 et 10K Flex), VRAMs, Controleur Interface PCI AMD, Tools Altera, ORCAD