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Aperçu des emplois de Tahar,
freelance CADENCE résidant dans l'Essonne (91)

• Aboundlogic - Bièvres (Paris area) Analog and mixed signal IC design engineer
  Jan 2009 - Jan 2010

  Responsibilities include: specifications review, architecture research, design, layout, pre and post-layout simulation as well as lab measurements. Design of the next generation IO comparator supporting a wide range of wired communication standards. The silicon proven performances achieved were: low power (200µW), rail-to-rail operation (wide swing and common mode range), high speed (400ps response time), low distortion @ maximum frequency (output duty cycle error less than 4%).
  Technology: tsmc 45nm

  _Cadence IC design suite with Eldo simulator_

• Wipro – Newlogic, Lustenau (Austria) Analog and mixed signal IC design engineer
  Jan 2007 - Jan 2009

  Responsibilities include participation to feasibility study, specifications assessment and review, analog/mixed signal design, documentation, design review, and layout supervision. Acquired knowledge in ∑∆ modulators, comparators, operational amplifiers, voltage and current references.
  Design experience:
   Re-design of a LDO for sensor automotive applications (Micronas), architecture changes have led to a better frequency compensation scheme, increased PSRR(>85dB up to 1MHz) and reduced quiescent current (<15µA), basic functionality was checked to be working on silicon.
  Technology: Micronas High voltage 0.45µm
  Tools: Cadence IC design suite with Spectre simulator.
   Design of a programmable 5Ghz VCO for very low current consumption or very low phase noise frequency range:[4.6GHz, 5.2Ghz] phase noise: [-108dBc @100khz, -128dBc @1Mhz] (when consuming 4.4mA)
  Technology: tsmc 90nm
  Tools: Cadence IC design suite with Spectre simulator.
   Design of a low power variable gain amplifier for mobile audio application (NXP) achieve a THD lower than -70 dB for a gain range between -24db to 29 dB in 21 steps, input referred noise less than 5µVrms consumes less than 300µW.
  Technology: C050_PMU
  Tools: Cadence IC design suite.
   Design of a thermal asperity detector for Hard disk read channel for (STMicroelectronic). Asperity resulting as a DC corruption is detected through the use a programmable filters and thresholds at the input of a high speed comparator (1.8ns response time max for less than 1mW).
  Technology: St 65nm
  Tools: Cadence IC design suite with Spectre simulator.

• NXP research labs - Eindhoven (Netherland) Research engineer (intern)
  Jan 2005 - Jan 2006

  Design of a variable ratio charge-pump DC/DC converter for Mobile Integrated power management applications.
  High level feasibility study and efficiency investigation
  Development of new theorem addressing a specific type of topology.
  Circuit design, and analysis of a scalable architecture.
  Technology: C050_PMU
  Tools: Matlab, Cadence IC design suite with Spectre simulator.

• Jan 2004 - Jan 2004

  Research stay at the Laboratory of Electronics and Computer Systems (LECS), Royal Institute Of Technology, Sweden. The investigations have lead to a novel transient fault detection equation/algorithm for digital FIR filters
  Implementation of the novel algorithm in VHDL and synthesis superior transient fault detection capabilities proven in simulations.
  Tools: Matlab, Modelsim, synopsis synthesis.