CV/Mission Altera freelance

Aperçu des emplois de Davide,
freelance ALTERA habitant les Alpes-Maritimes (06)

Expérience professionnelle

(2008 > present)
Function: Experienced ASIC Digital RTL Designer Engineer - Freelance
After my last experience as permanent consultant I became interested in working as Freelancer in
Europe; in parallel, after a marketing investigation in the south of France, I spent my energy in trying to
create a business activity in order to help the semiconductor companies to develop their ASIC systems.
I also worked at home developing some RTL modules to sell directly to the clients, as development of :
• 1Gb DDR2 SDRAM controller.
• Data-Link-Layer for the PPP Protocol over Ethernet (PPPoE) RFC-2516, Sw/Hw trade-off .
Currently Independent Freelancer, used to work closely with management, often involved in customer
meetings. Expert in the area of RTL conception and development for ASIC & SoC, with particular
attention to Speed and Power optimization; typically:
• Hardware accelerators for data-path
• Pipeline Architectures
• Smart Finite-State-Machines for algorithms development, functions and data-conditioning
• Asynchronous interfaces, generic or customized fast interfaces solutions
• IPs Low power architectures

Hereinafter latest meaningful contracts:
(Apr-2021 > present)
Company: Confidential - remote
Function: Principal ASIC RTL Designer - Freelance
Subject: Part-time freelancing supporting the Digital ASIC team for RTL development -
supervisor for concept improvement of my previous design project, 5G.

Technical Environment: Linux, Windows NT, Synopsys, SpyGlass, Cadence, Clearcase, Visio,
SystemVerilog.
(Aug-2021 > Jul-2022)
Company: Infineon - remote
Function: Principal ASIC RTL Designer - Freelance
Subject: Time-of-Flight 3D Camera project: In charge for the RTL development of the new
DVGA-Sensor-Matrix Readout Control unit and Exposure Control unit: controllers for
ADC, Sensor, DAC and Exposure. Plus RTL development of a Motion Detection
support unit, compensation of ADCs results. Improvements of: existing memory
controller for a new access mode for the mems ping-pong and a Frequency ramper
generator. Participating also to the validation of my developed RTL through linting,
debug and supporting the verification & firmware teams to correctly build their testcases
and FW codes involving my modules through the analysis of their failing tests.
Documentation update.
Davide ******** CV - 2023
Technical Environment: Linux, Windows NT, Synopsys, SpyGlass, Cadence, Modelsim,
SuperLint, Clearcase, Jira, Visio, Jama, SystemVerilog.

From (May/2020) to (October/2020)
Company: Qualcomm UK
Function: ASIC RTL Designer Engineer
Subject: Supporting the ASIC RTL team for the IoT audio system development of a smart
wearables technology. Involved in all the different ASIC steps.

Technical Environment: Linux, Windows NT, Synopsys, SpyGlass, VCS, Clearcase, Visio.

From (October/2017) to (March/2020)
Company: Ericsson – Sweden & UK
Function: ASIC RTL Designer Engineer
Subject: Supporting the ASIC RTL team for the 5G system development. In charge for the BB &
Radio Controller Subchips & Subsystems Integration (CCCR, EVC, GPIO_CTRL, SPI, LED,
Synopsys I3C Master & Slave DW IPs, PA_CTRL, SYNC, AXI_CTRL_UART, DB_UART, NIC400).
RTL development and modification of internal IPs and Filters Dynamic Power Save
optimization. Writing Design Specification documentation. Supporting verification &
validation.
Davide ******** CV - 2020
Technical Environment: Linux, Windows NT, Cadence, Synopsys, Clearcase, SpyGlass, Spectre,
Visio, Wavedrom, Hansoft Agile, Mantis.
From (June/2017) to (August/2017)
Company: Ensilica – London
Function: ASIC Designer Engineer
Subject: Supporting the ASIC team going to the tape-out for a mixed-signal ASIC.
Technical Environment: Linux, Windows NT, Cadence

From (May/2016) to (July/2016)
Company: Confidential – Italy
Function: ASIC RTL Designer Engineer
Subject: Supporting the RTL design team for the front-end ASIC design flow
Activities: Writing design specifications, RTL conception and Verilog development of:
asynchronous interfaces for fast data exchange – data path blocks – RTL modifications
for Power optimization - blocks integration – block level testbench – simulation –
synthesis scripts
Technical Environment: Unix, Windows NT, Cadence, Synopsys

From (September/2015) to (December/2015)
Company: Contractor in S3 Group – Prague - CZK
Function: ASIC Digital Designer Engineer
Subject: Supporting the RTL design team for the development of a mixed-signal fingerprint SoC
ASIC based on Cortex-M0
Activities: Writing design specifications, RTL conception and Verilog/System Verilog
development of: clock/reset/power management unit - dft controller - modules
modelling - digital thermometer - srams integration
Technical Environment: Unix, Windows NT, Cadence, SVN, ClearCase, Visio, Wavedrom

From (July/2014) to (February/2015)
Company: Contractor in Imagination Technologies IMGTEC – London - UK
Function: ASIC Digital Designer Engineer
Activities: Supporting the Video H265 Encoder RTL design team for the ASIC design flow, VHDL
Also Supervisor of main activities and designers
Technical Environment: Unix, Windows NT, Cadence, Synopsys, P4V, Jenkins
From (February/2014) to (April/2014)
Company: FXCM – New York - US
Function: App developer for a Foreign-Exchange-Market (FOREX) Multimedia Platform
From (January/2013) to (April/2013)
Company: Confidential
Function: ASIC Digital Designer Engineer
Activities: RTL development and VHDL coding of a JPEG Encoder with Pipelined Parallel
Architecture.
Technical Environment: Unix, Windows NT, Cadence
From (Febraury/2007) to (April/2008)
Company: ASTEK Consulting Group / NXP-Philips in Sophia Antipolis - France
Function: ASIC/FPGA Designer Engineer
Subject: Consultant in NXP-Philips to support the RTL design team developing sub-blocks for a
Bluetooth digital receiver.
Activities: Old architecture improvement - data bus control interface, Clocks & Power management
unit RTL conception and VHDL development - Top level integration - test bench
development - simulation - Top porting and Quartus synthesis on Altera FPGA -
drawing up user manual and release document
Technical Environment: Unix, Windows NT, Cadence, Quartus Altera FPGA
From (may/2000) to (febraury/2006)
Company: STMicroelectronics in Milan-Italy
Function: ASIC Digital Designer Engineer
Activities:
-Responsible for: proprietary AS-DSP micro-architecture RTL development, peripherals, IPs and SoC
subsystems conception and implementation for different customers: cores, cache memories, TCM,
Memory-Bists, Bus, Peripherals.
-Conception and development of a Co-Processor for the fft, Hardware Accelerators for Data Path.
-ARM cores and peripherals SoC implementation: A7s, A926, A946, L210 cache-controller, AMBA.
-IP blocks conception, implementation and verification, top-level integration for System-on-Chip,
typical peripherals: FIFO, Event-Counter, Frequency-Capture, Timer, GP-IO, Serial&Parallel-IO,
I2S, I2C, Interrupt-Controller, PWM/PDM/Stepping Motor-Control, Watch-Dog, Mailbox, Bridges,
Devices-Wrappers, Clock/Reset/Power Manager.
-Multimedia SoC Platform for NOKIA Mobile (NOMADIC): Core Subsystem RTL development and
implementation.
Involved in the Front-End design flow:
-RTL conception, VHDL & Verilog development
-Test-bench development, RTL simulation
-Synthesis (internal Clock-Gating, memory Bist, Scan Chains insertion, ATPG coverage)
-Formal Verification RTL-Gate
-Gate-Level simulation
-Different technologies synthesis: High Speed, Low-Power, High Density
Partnership:
- Motorola and Texas Instruments: to test new Low-Power and High-Density technologies, multiple
synthesis tests
5/6
Davide ******** CV - 2020
- ACCENT: to develop subsystems for a Smart-Sensor-Device
Technical Environment:
Main SYNOPSYS and CADENCE design tools for synthesis, simulation and verification:
Synopsys:
Design Compiler (Chip Synthesis)
Physical Compiler (Cell Placement)
Formality (Equivalence Checking)
Primetime (STA)
TetraMAX (ATPG – Patterns Generation)
VSS (Simulation)
Cadence: NC-Sim, compiling
Mentor-Graphics: Model-Sim
Assembly
Unix, Windows NT, main Windows Software as Office (Word, Excel, PowerPoint)

From (05/2008) to (today)
Company: Freelancing
Function: Digital Designer Engineer

After my last experience as Consultant I became interested in working as Freelance in Europe; in parallel, after a marketing investigation in the south of France, I spent my energy to try to create a business activity as Self-Employed in order to help the companies to develop their ASIC systems.
I also worked at home developing some RTL, using the Quartus tool by Altera to validate/synthesize the HDL code and to simulate with Modelsim.
Mainly peripherals and systems I developed by myself :

• Development of a 1Gb DDR2 SDRAM controller in VHDL.

• Study and development of the Data-Link-Layer (DLL) for the PPP Protocol over Ethernet
(PPPoE) RFC-2516, study trade-off Sw / Hw .

From (febraury/2007) to (april/2008)
Company: ASTEK Consulting Group / NXP-Philips in Sophia Antipolis - France
Function: Digital Designer Engineer
Subject: Consultant in NXP-Philips to support the design team with developing sub-blocks in a
Bluetooth digital receiver.

Activities: Role involves:
• Modify the old architecture, specifications given, develop the RTL blocks
• Top level integration, test bench development and simulation
• Porting on Altera Fpga and synthesis with Quartus
• Written the User manual and Release Document
Primary activities include the RTL conception and the VHDL coding for the new blocks, test-bench for simulation. Involved in the Clocks manager development to obtain reduction in Power consumption and in the development of a Data-Bus control interface.

Technical Environment:
UNIX OS, Windows NT
CADENCE
QUARTUS ALTERA FPGA tool

From (may...