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Photo de Sadi, Ingénieur Télécom VHDL

Sadi Ingénieur Télécom VHDL

CV n°200714C001
Études et formations

Accomplished Senior Digital Electronics Engineer, worked on multi-million gates ASICs Design as well as large scale FPGAs for various application. Strong of my 19 years’ experience in the industry, my involvement ranges from architectural definition, functional spec-ing, to HDL coding, Test-benchs, logic Synthesis ASIC/FPGA builds, constraints/timing closure, up to lab on target validation. I also lead team of Designers and worked with third party Design houses/Silicon partners. Excellent analytical and problem-solving, active team player and highly motivated self-starter. I worked on ITAR based projects and Hold Baseline Personnel Security Standard (BPSS).
Proficient in RTL coding: in either VHDL, VERILOG or System-Verilog.
System Verilog OOP & UVM. Functional verification & construction of self cheking test-benches
Translating DSP algorithms into HDL optimized Design. Wide experience in L1 physical layer implementation and Hardware accelerators. Making use of MATLAB & SIMULINK.
Low level embedded software development: C, Assembler for ARM CPUs. Linux(yotco, petaliux).
FPGA Development: Comfortable with Xilinx(Zynq), Altera and MicroSemi FPGAs. Hands with FPGA development, making Use of Qsys, IP integrator & SDK for embedded development.
ASIC Development: Strong ASIC development foundation built while working with big semiconductor companies like PHILIPS, NXP & ERICSSON.
High Speed Serial: PCIE Gen 2, Aurora, CPRI, SATA, ETHERNET (TCP/IP), DDR3 & DDR4
Digital interfacing: multi-channels double rate high bandwidth ADC/DAC for data acquisition, Sensor & closed loop control.
Logic Synthesis & STA: SYNOPSYS DC for ASIC, Simplify pro/Quartus/Xst for FPGA. STA Primetime for ASIC/ Time Questa for FPGA.
Lab exposure: experience with lab equipment like oscilloscope, Logic & Frequency analyzer, ESG & signal generator.
Bus Protocols: AMBA AXI-4, CAN, ARINC429/629, Mil1553-B, Altera-Avalon…
Scripting & Data-Base management: Scripting using Python, C-Shell, TCL, Perl, sed, SVN tortoise, ClearCase, Synchronicity & Perforce, Git Hub, IBM-ALM.
Standards: Wireless Telecoms LTE, 3G, ECSS, DECT
Modelsim SE 10.x, Ncsim v8, Synopsys VCS, CVE – XRAY, SPECMAN, ISE, Vivado/Alter Quartus /Symplify Premier/ libero IDE, Synopsys Design Complier/Prime (DC/PT), MATLAB/Simulink,
1997 – 1999: Master degree in Electronics engineering. Graduated from PIERRE & Marie CURIE University, Paris 6, Paris. ********.html
1994 - 1997: Bachelor degree in Electronics between SHERBROOKE university (Quebec, CANADA) and MULHOUSE university(France). ********

Expériences professionnelles

07/2019- 04/2020: GE Aviation, in Cheltenham. Senior FPGA Consultant FPGA Design Consultant, working on legacy safety critical Closed Control Loop System for aircraft entering manufacturing.
12/2018- 06/2019 : TDK-Invensense, Senior ASIC Consultant working on the Digital Processing Signal Path for Motion Sensors. Senior ASIC Designer Consultant, worked on low power Mems Montion Sensors ASIC for mobile phones, aimed for mass production. ASIC is digital-analogue mixed mode.
Languages & EDA: SystemVerilog, UVM, Simvision, Genus. Simulink, lint, ClioSoft & JIRA.
10/2017- 11/2018: Safran, Pitstone. Senior FPGA Consultant Working on CH53K Military Program. Involved in the Design and Verification of Power Generator for a Helicopter in line with DO254 DAL A.
Languages & EDA: VHDL, TCL, Altera Cyclone V & Arria V, Quartus 17, NIOS II, Eclipse, C software, GIT-hub, MicroSemi IGLOO-2, Questasim.
PROJECT 1: Data Acquisition Unit using Arria V FPGA.
Redacted FPGA implementation and Architectural spec derived from the client product requirement. Partitioned the architecture in Software & Hardware.
Used QSYS to create comprehensive embedded platform using NIOS II Safety Critical. Designed Software-Hardware interface between custom logic memory mapped registers and the NIOSII. Generated BSP and wrote the initial software and low-level drivers in C.
Designed Part of Mil1553-B from scratch. Conducted test & verification.
Built top-level including NIOS Subsystem & Custom Designed logic. Integration of several blocks eg: Arinc429, Hydraulic Sensors, RS422 to construct the system.
PROJECT 2: CH53K Generators composed of 3 IGLOO II FPGAs.
Worked on the verification of CH53K in line with DO254 DAL-A using VHD.

11/2016- 09/2017: GE Aviation, in Cheltenham. Senior FPGA Consultant FPGA Design Consultant, working on Boeing next generation of aircraft 777x serie. Project is Flight Recorder that goes into cockpit for Safety & critical DAL-A.
Languages & EDA: VHDL, TCL, MicroSemi IGLOO2, Synplify pro, Libero Soc, Modelsim.
PROJECT : Flight Recorder Unit.
Designed and verified, in VHDL, Registers Block Unit for the Recorder.
Specified & designed the physical layer of Boeing ARINC-629.
Responsible for the integration and building the firmware using Synplify & Libero.
Code inspection in line with DO-254 and GE guidances.
03/2016- 11/2016: Thales space, in Crawley. FPGA Design Consultant, working on prototype equipment for airplanes to enable mobile phone communication and WIFI while the plane is flying.
Languages & EDA: VHDL, TCL, Altera Aria v FPGA. Quartus, Modelsim, Matlab.
Some of the tasks:
Architected, Designed, verified and integrated an interface to ARINC 429 chip.
Evaluation of PCIE-Express Soft-Ip form third parties and designed the custom logic associated with it.
Designed an Interface between the FPGA & an external Modem.
Conducted FPGA integration using Quartus Qsys with HPS running.
Built the project & responsible for the time closure. Provided Firmware releases.
05/2015- 01/2016: Toshiba technology. FPGA consultant, worked on SATA solid state hard drive (SSD) ASIC to use in tablets and mobile handset.
Languages & Tools: Verilog, SystemVerilog, Tcl . FPGA Devices: VIRTEX6, KC705 evaluation board, using kintex 7 VIRTEX ULTRASCALE XCVU095. Synplify premier, Vivado release 16, Synopsys DC, PT and VCS. Linux.
Task #1: build a prototype to provide the firmware a platform to develop software and demo the product. The platform uses 4 Virtex-6 devices to fit all the logic communicating through Aurora link. Some of the tasks completed.
Converted Verilog HDL code from ASIC to FPGA. Generated Xilinx primitives, IO’s ports and necessarily code modification. Worked on dedicated Clock & Reset blocks for FPGAs. Designed some interface to communicate between FPGA’s, like AURORA link. Generated SATA High Speed Serial and integrated it.
Wrote timing constraints and conducted the Synthesis. Made releases.
Task #2: Using Xilinx UltraScale VCU108 to validate some advanced features like DDR4 that can’t be done with Virtex6. Some of the tasks completed.
Constructed HDL code to run RAM-DISK in XCVU095 FPGA.
Regenerated Xilinx Primitives from Virtex 6 to Ultrascale Virtex.
Ported the DDR4 and SATA Phys to Ultrascale Virtex.
Task #3: Conducting ASIC synthesis using Synopsys DC and Static Timing analysis.

2013 - 2015: ComDev International, Aylesbury UK. As principal Engineer, worked on AIS satellite receiver for marine traffic surveillance, position tracking and space mission. Worked on two projects, RCM (Radar Constellation Mission) & RADE (Reconfigurable Automatic Identification System) commissioned by European space agency.
EDA/Languages: Modelsim DE 10.3, Libero, svn, MicroSemi FPGAs: ProASIC3L/ProAsic3E: A3PE3000L & M1A3PE3000. VHDL & TCL for scripting.
Some of the work accomplished :
Coded several blocks, like ADC High bandwidth, with 8 differential LVDS channels, the serial data stream operates at 350Mhz. Control logic based and ECCSDS packets format. Integrated CAN BUS and designed an interface to exchange data with CAN and process the events. Top-level integration and verification.
2010- 2012: Alcatel-Lucent: FPGA lead Engineer. Worked on 2 major projects: Lead the development of LTE Remote Radio Head NG3 2.4 GHz utilising Altera Startix EP4SGX110. Participating in development of another Remote Radio Head, target it for CDMA 700Mhz, utilising Xilinx Kintex XC7.
EDA/Languages: Modelsim 6, Quartus 9.1/11.2/VIVADO v14.2, startix (EP4SGX110/EP4SGX180)/ XILINX Series 7 Kintex XC7K, Matlab and Lab instruments, SVN. VHDL/VERILOG, Matlab, Quartus, Qsys, TimQuest, VIVADO. Avalon + AXI4.
Some of the work accomplished :
Block level Design: Designed several modules in Uplink/Downlink chains like, Tx RMS per career power meter. Tx digital gain per diversity and LTE scalar. Gain prediction control block to scale up/down the signal magnitude dynamically. Integration of Digital Up Converter & Digital Down Converter filters. Fast AGC & SPI bus. Used MATLAB to generate test vectors for functional verification.
Worked on the CPRI, fast serial link connecting the Remote Radio head to base station through an optical fiber.
Ethernet TCPI/IP over CPRI. Integration of MII along with CPRI and routed traffic to external MAC.
Integration of Altera Triple Speed Ethernet for different project.
Integration of DDR3 memory controller and built a test-bench.
ADC interface: Designed dual channel Rx ADC interface, the incoming serial LVDS data runs at 245.76Mhz. Also coded DC removal filter. DC tone, 0 IF, is introduced by ADC.
Integration & Verification: Integrating various blocks. Worked alongside verification engineer to construct test cases and verify the Design.

2006- 2010 : Ercisson, EMP. As Senior ASIC Engineer, worked on ASIC made of (WCDMA/EGG/GSM)MODEM subsystem containing 2 cores ARM926 and DSP. The modem is connected to an off-chip base-band that has an OMAP open OS. The full solution go into a single stacked die to die package to make a smart phone.
HDL language/EDA: VHDL, Modelsim 6.3c, Seamless-CVE, X-ray debugger, DesignSync for ASIC, ClearCase for SW, PrimeTime PT, Source Insight, Eclipse, FIDO, Linux/Windows2000. C code.
Some Work packages:
Porting the ASIC into a new technology. Replacement of memories, IO pads, analogues macros, primitives and management of pinouts changes.
Designed some blocks in the modem, like turbo encoder, 3G ciphering and deciphering, communication between DSP and ARM-CPU.
Integration of the on chip ARM9-CPU and the interconnect.
Worked on the Boot up Sequence and code execution.
Conducted the Integration and Verification of a modem and application processor.
Wrote Embedded C software routines, data structure library. Wrote test-cases to verify data path.
Gate level Simulation post CTS netlist & Scripted the flow in C-SHELL.

2004- 2006: (SunCorps, UK). ALDERSHOT, HAMPHIRE. Principal Design Engineer. The project was cordless phone using DECT for voice and BLUETOOTH for video. The project was a system on Chip SoC based on ARM 11 CPU for High end market.
language/EDA: Modelsim, Precision, Vertex2, ISE, Realview, C & assembler & VHDL.
Some Work packages:
Responsible for DECT IP, (Digital Enhanced Cordless Telecommunication)
FPGA Lead. Prototyping the ASIC.
Modified RTL for FPGA & built a top-level wrapper to connect the FPGA to an off chip ARM CPU. Managed the clock generation/reset, pinout and core conversion from ASIC to FPGA.
Wrote initial SW to boot up the CPU, the main and different handlers.

2000-2004: PHILIPS SEMICONDUCTORS. Located in Sophia, Nice, France. As ASIC Engineer, Worked on handset Base-band for GSM + GPRS, and a 3G modem. Took part in different steps of concept: RTL coding, verification, prototyping, synthesis/DFT and validation in LAB. C & assembler code.

Some of the work packages: Designed and verified several algorithmic modules for 3G modem. HDL language/EDA tools : VHDL, NNCSIM, Certify, ISE Xilinx, Vertex 2, DFTAdvicer, cadence PKS.
Designed several modules: Rake Receiver, AGC, Sleep Timer, UMTS universal Timer, 3G USIM Interface, GPS interface to the Base-Band.
Built block level test-bench for each module, used C reference code to generate input/output vectors.
1999: IBM. Paris, France. Internship in High Debit Network department SONET/SDH.

2020: Python, UVM.
2018: System Verilog & System Verilog Oriented Object.
2013: DOORS, Scrum agile training, Altera Qsys/SopC builder.
2010: LTE Training, Quartus 9.1/TimeQuest. 2007: SPECMAN eVC. 2005: ARM11 (at ARM Cambridge office. 2004: Embedded C software. 2003: ARM9(Hardware, Software). 2002: 3G+, Cadence PKS. 2000: Synopsys DC/STA.