Pierre - Développeur VHDL

Work Experience

Oct 2018
– Sep 2019
(1 year)
Enviroearth, Aix en Provence, France – Project Manager
Project management, including clients and subcontractors interfaces in a highly
international environment.
Monitoring stations:
 Design of an electrical and communication upgrade of a standalone
infrasound monitoring station (PV, Ethernet and Radio communication, ...).
 Site survey, Bid preparation and project management of the installation of a
new radionuclide monitoring station in Salta, Argentina.
 Upgrade of an infrasound monitoring station in Palau.
 Installation of an infrasound monitoring station in Argentina, including
communication (optical fiber) and power connection.
 Upgrade of an infrasound station in Bermudas.
 Electronic PCB board design.
Renewable energy:
 Bid preparation, site survey and design of a 38kWp solar hybrid plant in Port
Au Prince, Haiti.
 Consulting on an existing <1kWp standalone PV installation, to upgrade the
system according to the load requirements and the local regulations.
 Follow-up, initial tests and remote installation of a monitoring solution for
energy plant with real time feedback in Tanzania and Malawi.

Oct 2017
– Apr 2018
(7 months) Accelize, Aix en Provence, France – FPGA engineer
Vendor-agnostic tool development for server-based FPGA applications.

• Verilog generation scripts (Python) of memory blocks (DDR, SRAM, AXI, Avalon).
• Python script of Xilinx Microblaze and Intel NIOS II soft processor integration flows.
• FPGA design (Verilog) on Amazon Web Services (AWS) cloud on Xilinx Ultrascale+.
• RTL design in Verilog of a memory-based AXI4 to AXI4Stream bridge with embedded DMA. Optimized for the highest data transfer rate in AWS framework.
• RTL verifcation with SVUnit framework in SystemVerilog.
Apr 2016 – Mar 2017
(1 year) CEA DASE, La Paz, Bolivia – International Volunteer

• Technical on-site maintenance, upgrade, and emergency interventions on seismic and infrasound stations in Bolivia.
• Network management at the seismic National Data Center (NDC).
• Event extraction and analysis of infrasound data (explosions, volcanoes, tides, storms) with DTK PMCC tools.
• Design and deployment of a low-cost 3G-based real-time transmission system for seismic stations.
◦ Network management on Raspberry Pi and CISCO devices.
◦ PCB design of a Raspberry Pi daughter sensor board (voltage, temperature, relays).
◦ Database (MySQL) server deployment.
◦ Web-based interface to monitor station network state in real time (HTML PHP, MySQL).

Feb 2014 – Mar 2016
(2 years) EASii-IC, Grenoble, France – Radiation Test Engineer

• FDSOI 28nm chip radiation characterization (neutrons, alpha, muons, heavy ions).
• FDSIO 28nm chip temperature and low voltage characterization.
• VHDL design on Xilinx Virtex5 of the chip tester:
◦ Custom GPIO based interfaces (parallel and multiplexed interface) towards test chips.
◦ JTAG interface to program ARM and Leon processors
◦ Xilinx Microblaze soft processor integration.
• VHDL design of an ARINC-818 driver on Xilinx Zynq.

Nov 2013 – Feb 2014
(3 months) Maya Technologies, Aix-en-Provence, France – FPGA Designer

• VHDL design of an airborne engine control system on Microsemi FPGA with DO-254 standard.
• Elaboration of the specification and architecture documentation.

Jan 2012 – Jul 2013
(1,5 year) BitSim AB, Stockholm, Sweden – Hardware Engineer
Creation of an autonomous seismic data logger system.

• VHDL design of SDIO, SPI and UART interfaces and DAC/ADC drivers on Microsemi Igloo FPGA.
• C code (SPI, Ethernet) development with FreeRTOS on STM32 processor.
• PCB design (USB, Ethernet connections) with Eagle PCB Design.
• GUI design with C++ Qt Framework, with database management and network communication.
• Network management on Unix systems with protocols NTP, TFTP and Telnet.
• Continuous integration flow setup with Jenkins.
• Post production test definition, implementation and follow-up.

Jun 2011 – Dec 2011
(6 months) ST-Ericsson, Sophia-Antipolis, France – DfT Engineer intern –Master thesis
Creation and validation of a Synopsys flow to wrap IPs with an IEEE1500 test wrapper.

• Tcl script of the IEE1500 wrapper generation for Synopsys DfT Compiler flow.
• Flow application on state of the art ST-Ericsson chip design.
• Pattern generation with ATPG tool Synopsys TetraMax.
• Simulation under Cadence NCSim.

Apr 2011 – Jun 2011
(3 months) KTH, Electronics Systems department, Stockholm, Sweden – Research work
Design and evaluation of router component models in Spintronics.

• Design of spintronics components (MTJ) Spice models.
• Spice simulation of network buffer and crossbar in CMOS and with MTJ.
• Publication and speaker presentation at the Network-on-Chip Symposium.

Jun 2009 – Aug 2009
(3 months) ST Microelectronics, Crolles, France – Worker internship
Chip production in clean room and preventive maintenance on etching machines.