Abdelilah - Freelance VHDL

Expérience professionnelle

Since June 2005
 Lead Tech Design – Casablanca
Responsible of DESIGN Team: Project & team leader (team of 6 people)
• Team management & animation
• Project management
• Definition & tracking of project / team planning
• Responsible for the delay/quality of deliverables and the project cost
• Design of embedded systems and technical support team / customer
• Architecture proposal, RTL Coding, Simulation & Platform validation
• VHDL, Verilog, Embedded C
• Design FPGA, Altera, Xilinx, DDR/DDR2 memories management
• Digital TV, video pre-processing, IPTV, Broadcasting, Telecom

Many projects conducted successfully for the account of Thomson Grass-Valley:
Telecom: (IPTV, TS, protocols: RTP/UDP/IP – Ethernet)
VOIP (4 month -5 people):
• Integration & test of FEC functionality
• Video/Audio Transmission/Reception over IP
• System generation & RTL coding
• simulation, validation, Integration and test on Platform
• Tools & Materials : Ethereal, StreamXpert, DekTec, NetDisturb

VMIP (4 month -4 people):
• Multi-encapsulation of video/audio over IP
• Variable/Constant Bit Rate modes, MAC implementation
• Architecture proposal, RTL Coding
• Simulation, validation, Integration & test on Platform
• Tools & Materials : Ethereal, StreamXpert, DekTec
Digital TV: (MPEG2/ MPEG4, SD/HD, TV broadcasting)

Noise reduction(8 month -6 people):
• Design of noise reduction system for professional video
• NIOS system Generation & Development of a NIOS Shell (Embedded C)
• Architecture proposal, RTL Coding
• Simulation, validation, Integration & test on Platform
• Tools & Materials : StreamXpert, StreamXpress, DekTec, Spectrum board

SD_Mustang (6 month -4 people):
• Integration of Audio IPs (AES, Audio de-embedding)
• Adding PVR functionality in the TS packets (used by pay TV channels)
• Architecture proposal, RTL Coding
• Simulation, validation, Integration & test on Platform/evaluation Board
• Tools & Materials : StreamXpert, DekTec, Audio/video generator/analyzer

HD Downscaler (3 month -3 people):
• Video downscaling from HD format to SD format
• Architecture proposal, RTL Coding
• Simulation, validation, Integration & test on evaluation Board
• Tools & Materials : Video SDI generator/monitor

SD/HD_PRIME (10 month -4 people):
• Motion estimation for Standard/High Definition video
• RTL Coding, simulation, validation & test on Platform
• Tools & Materials : StreamXpert, StreamXpress, DekTec, Spectrum board

Oct. 2003-April 2005
 STMicroelectronics – Rabat
• Design engineer of mixed IC in DLL team (Delay Locked Loop):
• Analog flow: design of analog blocs (schemes and layout on Cadence, electrical and post-layout simulation with Eldo)
• Digital flow (Asics): VHDL, Verilog, synthesis and STA (Synopsys), simulation (NCsim), P&R (Astro)
• Technologies: HCMOS9, CMOS90, CMOS65

SATA – SERDES (CMOS90& CMOS65)
• Design, simulation & layout of different blocs of DLL (750 MHz)
• Design, simulation & layout of transmission line to propagate the clock generated by the DLL
• Tools: Cadence, Eldo

DLL memory Test-chip (HCMOS9 & CMOS90)
• RTL coding, synthesis, and P&R
• Tools: NCsim, Synopsys(Design compiler, PrimeTime), Astro, Cadence

March – August 2003
 PHILIPS (NXP) – Caen (France) - training
Design of new frequency synthetizer which use only one oscillator to cover the band 90-900 MHz. (BICMOS technology, Architecture Proposal, design, electrical & post-layout simulation and Layout on Cadence). The proposed architecture were the subject of a PATENT filling.

March – June 2002
 IMEP – Grenoble (France) - training
Design of a fractional frequency divider at 10GHz and under 1.2V in CMOS/SOI 0.12m technology for the account of STMicroelectronics. (Architecture Proposal, design & simulation on Eldo RF).