Bouchaib - Développeur VHDL

May 2019 – August 2019 Senior Digital Design Engineer Delair Aero
(Contract)
Main responsibilities: Micro-architecture. RTL code design – VHDL- IP integration-
Synthesis. Unitary Test bench Verification.

Project :

• Synchronisation of image capture for 6 camera
Language: VHDL– Tools: FPGA (Xilinx: Kintex 7, micro-blaze), Vivado, SDK

April 2019 Business Development for my own company
(1 month)
Main responsibilities: Create Company to work in free-lance

January 2019 – March 2019 Business Development Klanik
(4 months, Permanent)
Main responsibilities: Research opportunities in micro-electronics and embedded
Systems. Contact companies to know their need.

March 2017 – December 2018 Senior Digital Design Engineer Klanik
(21 months, Permanent) for Nexter Electronics

Main responsibilities: Micro-architecture. RTL code design – VHDL- IP integration-
Synthesis. Unitary Test bench Verification.

Project :

• Digibus Board dedicated to military application
• FPGA Design
 Interface and communication with TMS570(Texas Instrument)
• Read/Write Registers
• Watchdog
 Manage frame for subscribers and manager to send and receive them using serial protocol (Digibus GAM-T101).
 Interface PCIe Gen1 (IP Xilinx)



Language: VHDL– Tools: FPGA (Xilinx :Spartan 6), ISE, Synplify Active-HDL


May 2016 – January 2017 Senior Digital Design Engineer Klanik
(8 months, Permanent) for Uwinloc

Main responsibilities: Micro-architecture. RTL code design – Verilog- IP integration-
Synthesis. Test benches Verification. Lab evaluation (Validation on the board:
KCU105 and DAQ2)

Project :

• Localisation Indoor
• Sample data to 1GHz
 Configuration ADC, DAC, PLL(Daughter board DAQ2)
 Update reference design for our application



Language: Verilog – Tools: FPGA (Xilinx: Kintex 7), Vivado


November 2015 – April 2016 Business development Klanik
(6 months, Permanent)
Main responsibilities: Research opportunities in micro-electronics and embedded
Systems. Contact companies to know their need.Redact document
with Companies and Technical Manager.


March 2014 – October 2015 Senior Digital Design Engineer Klanik
(18 months, Permanent) for Alstom Grid

Main responsibilities: Micro-architecture. RTL code design – VHDL. IPs integration. Top and block level synthesis. Test benches Verification. Lab evaluation (Validation on the board) –
Documentation. Testbench development.

Project :

• Switch
• Test Procedure for Display board(Test led, display)
 Document
 RTL coding to display information about Test
 Update C code for microcontroller

• IP Communication Integration (Stack Flexibilis) .
Configuration, Test, Development
Add functionalities to give information on Display board (LCD, LED)

• Digital Process Unit (DPU) allow to manage information for electrical sub-stations
• Slave Card FPGA– Micro-architecture.
Communication with CPU in using C264 parallel bus.
Analysis of frame (Goose) from Digital Control Unit to send information to the CPU and generate
frame (Goose) from CPU Information to the Digital Control Unit.


• Digital Control Unit (DCU)
• Master Card FPGA– Micro-architecture.
Debug and add improvement.

Language: VHDL – Tools: FPGA(Altera), Modelsim, Quartus, IED Scout, JIRA for traceability

Jan 2012 – Dec 2013 Senior Digital Design Engineer SEA/TACHYSSEMA
(20 months, Permanent) for THALES

Main responsibilities: Micro-architecture. RTL code design – VHDL. IPs integration. Top and block level synthesis. Lab evaluation(Validation on the board) – Documentation. Testbench
development.

Project: Networking System based on FPGA board for datas transfer (informations, images)


• Network based on FPGA– Micro-architecture. Design Communication Management.
Synthesis and verification of the design. Validation on board (Application using Fiber Optic: High Speed :SERDES)
Language: VHDL – Tools: Active-HDL, Diamond 2.0

• Video Demonstrator – Lab evaluation, Debug,Updating, synthesis and verification of the design.
Language: VHDL – Tools: FPGA(Lattice), Active-HDL, Diamond 2.0

Project: Stack Processor

• Processor for FPGA – Micro-architecture. Design RTL code design - ALU, Timer, Interruption Management. Synthesis and verification of the design. Validation on board using UART
Language: VHDL – Tools: Active-HDL, Diamond 2.0


Apr 2011 - Sept 2011 FPGA Design Engineer Amesys for Sagem
(4 months, Permanent) Defense
Main responsibilities: Micro-architecture. RTL code design – VHDL. Testbench development. Documentation
Project: Calculator for avionics (standard DO 254)

• Block Reset and Synchronization Management– Micro-architecture. Design and Functional Verification. Document. Traceability of requirements
Language: VHDL – Tools: Modelsim, FPGA (Actel)


Jan 2010 - Mar 2011 FPGA Design Engineer MAScIR Microelectronics
(15 months, Permanent)
Main responsibilities: Put In place Embedded System Activity with Manager- Contact Providers-Specification . RTL code design – VHDL. IPs integration. Synthesis. Lab evaluation - Documentation. Testbench development.

Project: Demo board using FPGA, Video CMOS sensor , RAM,USB

• FPGA Architecture – Specification. Micro-architecture. Design (Debayer, Interfaces).Testbench development.
Language: VHDL – Tools: Modelsim, FPGA(Altera), Quartus II


Jun 2007 - Dec 2009 Development and Verification Engineer Amesys for
(30 months, Permanent) THALES ALENIA SPACE
Main responsibilities: Micro-architecture. RTL code design – VHDL. Testbench development. Validation Documentation.

Project: IP Video
Test Plan.Test bench. Design block to manage video data. Micro-architecture.

Project : Board dedicated to DVB RCS
Add functionalities (ACM Mode, RF loop, Continuous Modulation,Spread Preamble).
Specification. RTL code design – VHDL.
Language: VHDL – Tools: Modelsim, FPGA(Altera), Quartus II


May 2004 - May 2007 ASIC Design Engineer ST Microelectronics
(36 months, Permanent)
Main responsibilities: Provide Netlist Gate. Check automation.Regression test.Micro-architecture. RTL
code design – VHDL/Verilog. Verification

Project: IP TV
• RTL2Gates.Design Constraints. Update Script. Synthesis. Formal Proof
Language: Tcl – Tools: Design Compiler, Formality

• Verification .Test Plan (Standard video) - Script C-Shell.

Project: IP Video Post Processing

• Filter to improve image quality. Design RTL: Deblocking Filter (Standards in loop : H264 and VC1, Post filter : MPEG4 and DIVX6). Functional Verification (specman user, co-simulation using Ncsim and C-Model).RTL check
Language: VHDL – Tools: NCSim, Spyglass

Education

2003 Master's Degrees : Mastère Spécialisé SIME (Systèmes Informatiques et
Microélectronique) à l’ISMEA groupe ESIM (Ecole Supérieur
d’Ingénieurs de Marseille).

2002 Master's Degrees : DEA CCMM (Conception de Circuits Microélectroniques et
Microsystèmes), Toulouse