Ketra - Développeur et Intégrateur Systèmes Embarqués

WORK EXPERIENCE

Feb 2020- Present: WABTEC Faiveley Transport, TOURS, France
Embedded SW development and integration
 Embedded SW integration of a real-time onboard events recorder for rolling stocks on ATESS4G products equipped with SOM (System-On-Module) Spear NXP iMX-8 (contains ARM Cortex-A72 and ARM Cortex A-53).
 Software features development : Extension of events support for ASFA serial link using C on
ATESS3G legacy product (equipped with PowerPC).
 Problems troubleshooting, bug reproduction , bug fix, supplied fixes and code improvement.
 SW integration and test automations using Robot Framework RIDE and Python

October 2019- Jan 2020 : Automotive Systems Engineering training with AJC and Altran
 General intro training in the automotive field: CAN bus protocol , CANalyzer, CAPL programming, ISO
26262, ADAS, SysML, MBSE, DOORS, Matlab/Simulink

June 2015-Dec 2018: SEQUANS Communications, Colombes, France
Senior systems integration engineer for LTE SoC 4G Chipsets development
 HW/SW integrations of the SoC interfaces GPIOS, SPI, I2C, UART, Aux ADC temp sensor, UICC, HSIC,
SDIO, Wifi RTL 8192, SLIC
 Test plan documentations
 Analog design schematics analysis and ECO modifications (Engineering Change Order)
 Debug, Trouble, Boards bring-up , HW interfaces bring-up.
 LPM mode (Low- Power mode) bring-up in RRC Idle mode and measurement of the paging performance
 LTE Throughput tests with Iperf
 HW troubleshooting and ECOs
 LTE features integration with Maximum Power reduction with NS signalling

January 2014-Nov 2014: ERCOM (R-Interface), Marseille, France
SW integration consultant for 4G Multi UE Emulator (Mobipass)
 Precoding Matrix generation and implementation in C for SISO, TX Diversity and 2x2 MIMO
 Code optimisation with Intel SSE/AVX assembler instructions set on IBM BladeCenter server HS-23
 Timing Diagram script development in perl for Profiling Data Analysis of multicore activities on IBM Blade
Center HS-23
 Investigation work on the SW to take advantage of the multicore and parallelisation capability of the HS-23

April 2013-Sept 2013 : Intel Mobile Communications GmbH, Duisburg, Germany
3G-3,5G UMTS (W-CDMA FDD) Physical Layer Firmware Development Consultant
 DSDS (DualSim-Dual Standby) Firmware feature porting from legacy product Intel XMM6360 to new
product Intel XMM7260 in the Activity Manager Module
 Firmware trouble shooting, debugging (including on Lauterbach Trace 32)
 Firmware Bring-up on Virtual Prototype
 UTP Ticket analysis
 Firmware Log analysis
 Activity Manager Module test debugging and adapting
 Daily support for regression test

Sept 2011- present: Intel Mobile Communications GmbH, Duisburg, Germany
3G UMTS (W-CDMA FDD) Physical Layer Validation Consultant (consultant position)

• Verification of the DSDS (Dual Sim- Dual Stand-by) feature on the Virtual Prototype (a SW model of the chipset) of the 3,5 G modem.
• Verification of the R99 features
• Design and troubleshoot the testcases
• Execution of regression tests on new FW builds
• Daily troubleshooting , analysis, fault finding of the failed TCs and logs.
• Reporting errors and analysis to FW team

 
June 2007- August 2011: ST-Ericsson , Lund, Sweden
Software consultant: System verification SW development for 3G WCDMA FDD Physical Layer functionalities

• Design & Development of a complete Physical Layer WCDMA template library to drive the Anritsu MD8480C “Harikiri” with Ericsson Motapp tool. The scenarios MD8480C were developed in C and includes scenarios for R99 tests: P-CPICH, P-CCPCH, S-CCPCH, BCH, RACH, FACH, PCH, DL/UL DPCH, Compressed mode, Power control, UL DPCH bit-true test on payload. Also includes Release 6, Release 7 scenarios for HSDPA, HSUPA and HSPA+.
• Design & Development of a Physical Layer LTE template library (partly) to drive the Anritsu MD8430A “Harikiri” with Motapp. The scenarios DLLs for the Harikiri were developed in C and includes the scenarios for BCH, DL-SCH, PDSCH, PUSCH
• Design & Development in C of a WCDMA L2/3 stub module, WCDMA TeLO (Test Layer One, a SW stub to LAYER 2/3 to stress the PHY layer) to test the ST-Ericsson multimode chipset Physical Layer SW that includes the following services : Cell search, BCH read, RACH, FACH, PCH, DCH, HSDPA, EUL including the UL data generator, Compressed Mode, FMO, Measurement, RAT scan, RSSI scan.
• Design & Development in C of the ePHY emulation mechanism to replicate the request confirmation and indication primitives sent from PHY Layer to L2/3. This allows the physical layer testers to validate the script and test TeLO standalone before the feature is available on the target.
• Daily trouble-shooting, debugging, script writing, reproducing reported errors
• Daily support to physical layer testers and physical layers SW developers across different sites: Luleå (SE), Lund (SE), Nürnberg (DE)
• Executed baseband tests for Hassium and R13 chipset:
• Provided seminar & training to physical layer test team in Lund and Nürnberg site on how to use and develop the Anristu MD8480C Harikiri templates.


Feb 2007- June 2007 Atena Engineering GmbH, Munich, Germany
SW validation consultant

• SW modules verification for an Engine Protection and Monitoring Unit for the TP-400 turboprop engine for Airbus A400M. The end customer is MTU Aero Engines.
• The verification follows the guidelines of the aeronautical standard RTCA DO-178B
• Black box (functional test) , White box (coverage test), MC/DC test. Creation of test cases. Execution of test with MTU in-house testing toolchains. Fault finding in C code and in SW design document. Collection of results and reporting to customer.

October 2005- August 2006: BenQ-Siemens Mobile Phone GmbH, Munich, Germany
Embedded Software / Firmware developer (permanent position):

• Performance and conformance measurements of MPEG2- Layer 3, AAC, AAC+ audio codec on ARM development suite. Perl testscript development. Codec was provided from a 3rd party vendor and was subjected to automated tests with Perl testscript.
• Voice control firmware validation on SGOLD2 chipset: Setup testbench. Configuration of firmware. Validation of results with bit-true test.
• Porting of Ogg-Vorbis decoder on ARM926EJ-S with ARM Developer Suite 1.2 (ADS)
• Integration of Ogg-Vorbis decoder on Qualcomm 6280 chipset


July 2000 – October 2005 SIEMENS AG Mobile Phone, Munich, Germany
Physical Layer Firmware Developer (permanent position): Role covers the full lifecycle development and post-design support of firmware for GSM, GPRS, EDGE, and UMTS baseband chipsets.

• Design and implementation of firmware for rate ½ and rate 1/3 hardware viterbi decoder on FPGA for UMTS FDD chipset. Design and implementation of firmware for UMTS Blind Transport Format Detection (BTFD) on a FPGA for UMTS FDD chipset Infineon M-GOLD.
• Test vectors generation on GSM/GPRS/EDGE modem simulation chains with COSSAP: Full Rate, Half Rate, HSCSD, GPRS CS1-4, EDGE MCS 1-9, incremental redundancy for EDGE
MCS-9.
• Post-design support of UMTS Power Control on prototype board (Infineon-Siemens MGOLD chipset)
• Design a software testbench for an audio preprocessing path based on Virtual Prototype (a software model of the Infineon-Siemens SGOLD2 baseband chipset).
• Integration of GSM audio scheduler with GSM/GPRS/EDGE modem scheduler on SGOLD2 Virtual Prototype chipset.


March 1998-May 2000 MOTOROLA LTD, GSM Products Division, Swindon, UK
Physical Layer Firmware Developer (permanent position): Role covers full lifecycle development and post -design support of firmware for Micro and Pico Cell BTS using the V cycle.

• Full lifecycle firmware development of the GSM TCH/HR (half rate) channel codec on Pico Cell RF head BTS.
• Full lifecycle firmware development of the Adaptive MultiRate (AMR) TCH/AFS and TCH/AHS channel codec on Micro cell BTS
• Post-design support for GSM/GPRS modem firmware
• Development on Assembler on Motorola DSP 56305

March 1995-July 1995: ALCATEL-ALSTOM Research Center, Marcoussis, FRANCE
Analog Circuit Designer (industrial training): Project related to the TGV Atlantique high-speed train. Feasability study in the R&D department: Design of an active inductance with passive and active components which was used in an LC circuit to damp vibrations generated by a piezo-electric material.