Subject: Many-Core Architecture (EMCA) : scalable and energy efficient Radio-AccessNetwork (RAN) parallel compute networks for 5G/IoT. In charge for the RTL
development of innovative new features to improve multi-channels communication
between multiple CPUs / DSPs / Accelerators. I validated my implemented
microarchitectures through linting, sim debug and supporting the verification team to
correctly tune their testcases through the analysis of their failing tests. Project
specific documentation update.
Subject: SoundWire-I3S (SWI3S) Peripheral IP: In charge for the IP architecture conception
and RTL development of all the modules of the new MIPI Audio Interface Peripheral
unit used for transporting audio streams and control information frames together on a
single link in half/duplex fashion, single-ended PHY: Link-Controller, CommandTransport-Decoder, Payload-Controller for Audio Chip. Participating also to the
system validation through linting, debug and supporting the verification team to
correctly tune their testcases through the analysis of their failing tests. Participated to
the review of multiple MIPI Draft SWI3S draft specifications.
Project specific documentation update in Jama.
Subject: Time-of-Flight 3D Camera project: In charge for the RTL development of the new
DVGA-Sensor-Matrix Readout Control unit and Exposure Control unit: controllers
for ADC, Sensor, DAC and Exposure. Plus RTL development of a Motion Detection
support unit, compensation of ADCs results. Improvements of: existing
memory controller for a new access mode for the mems ping-pong and a Frequency
ramper generator. Participating also to the validation of my developed RTL through
linting, debug and supporting the verification & firmware teams to correctly build
their testcases and FW codes involving my modules through the analysis of their
failing tests. Documentation update
.
Subject: Part-time freelance collaboration supporting the Digital ASIC team for RTL
development-supervisor for concept improvement of my previous design project, 5G.
Subject: Supporting the ASIC RTL team for the IoT audio system development of a smart
wearables technology. Involved in all the different ASIC flow steps. SoC with ARM
Cortex-M3 core.
Subject: Supporting the IP & Radio-Controller team for the 5G system RTL development
of four chips.
In charge for the RTL new development or optimization/modification of existing IPs:
Event-Controller core, Filters Dynamic Power Save optimization, CCCR, EVC,
GPIO_CTRL, SPI, LED, Synopsys I3C Master & Slave DW, PA_CTRL, SYNC,
AXI_CTRL_UART, DB_UART, NIC400. Implementation of the four BaseBand &
Davide ******** CV - 2025
Radio Controller Subchips & Subsystems including the above IPs. Writing Design
Specifications documentation. Supporting verification & validation involving my
modules.
Subject: Supporting the ASIC team going to the tape-out for a mixed-signal Fingerprint ASIC
SoC with ARM Cortex-M3 core.
Subject: Supporting the ASIC team going to the tape-out for a mixed-signal Fingerprint ASIC
SoC with ARM Cortex-M3 core.
Subject: Supporting the RTL design team for the front-end ASIC design flow
Activities: Writing design specifications, RTL conception development of:
asynchronous interfaces for fast data exchange – data path blocks – RTL
modifications for Power optimization - blocks integration – Supporting validation
Subject: Supporting the RTL design team for the development of a mixed-signal fingerprint
SoC ASIC based on ARM Cortex-M0 core.
Activities: Writing design specifications, RTL conception and development of:
clock/reset/power management unit - dft controller - modules modelling - digital
thermometer – Macro with srams integration